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Features
* * * * * * * * * * * *
Supply Voltage: 8.5 V RF Frequency Range: 1400 MHz to 1550 MHz IF Frequency Range: 150 MHz to 250 MHz Enhanced IM3 Rejection Overall Gain Control Range: 30 dB Typically DSB Noise Figure: 10 dB Gain-controlled Amplifier and L-band Mixer Power-down Function for the Analog Part On-chip Gain-control Circuitry On-chip VCO, Typical Frequency 1261.568 MHz Internal VCO Can Be Overdriven by an External LO On-chip Frequency Synthesizer - Fixed LO Divider Factor: 2464 - Nine Selectable Reference Divider Factors : 32, 33, 35, 36, 48, 49, 63, 64, 65 - A Reference Oscillator (Can Be Overdriven by an External Reference Signal) - Tristate Phase Detector with Programmable Charge Pump - Programmable Deactivation of Tuning Output - Lock-status Indication - Test Interface
L-band Down-converter for DAB Receivers U2730B-N Preliminary
Electrostatic sensitive device. Observe precautions for handling.
Description
The U2730B-N is a monolithically integrated L-band down-converter circuit fabricated with Atmel's advanced UHF5S technology. This IC covers all functions of an L-band down-converter in a DAB receiver. The device includes a gain-controlled amplifier, a gain-controlled mixer, an output buffer, a gain control block, a power save function for the analog part, an L-band oscillator and a complete frequency syntheziser unit. The frequency syntheziser block consists of a reference oscillator/buffer, a reference divider, an RF divider, a tri-state phase detector, a loop filter amplifier, a lock detector, a programmable charge pump, a test interface and a control interface.
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1
Figure 1. Block Diagram
TH 17 AGC 18 19 IF VCC1 VCC3 VCC4 3 20 28 VCC2 9
Voltage stabilizer
GND 6, 7, 8, 21, 22, 23, 24
Internal 5 V supply voltage for frequency synthesizer U Analog part
Bandgap Lock detector
14
PLCK
RF NRF TANK VREF
26 25 5 4 Power save (analog part)
Power down Test interface
20k
VCO RF counter : 2464
Tristate phase detector Charge pump 200 m/300 m
12
CD
Reference counter : Nref
13
Control interface
PD
1 PSM
15 OSCB
16 OSCE
11 TI
10
27
2
CI SI1 SI2
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Pin Configuration
Figure 2. Pinning SSO28
PSM SI2 VCC1 VREF TANK GND GND GND VCC2
1 2 3 4 5 6 7 8 9
28 VCC4 27 SI1 26 RF 25 NRF 24 GND 23 GND 22 GND 21 20 19 18 GND VCC3 IF AGC
CI 10 TI 11 CD 12 PD 13 PLCK 14
17 TH 16 15 OSCE OSCB
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Pin Description
Pin 1 2 3 4 5 6, 7, 8, 21, 22, 23, 24 9 10 11 12 13 14 15 16 17 18 19 20 25 26 27 28 Symbol PSM SI2 VCC1 VREF TANK GND VCC2 CI TI CD PD PLCK OSCB OSCE TH AGC IF VCC3 NRF RF SI1 VCC4 Function Power save mode Control input Supply voltage VCO Reference pin of VCO Tank pin of VCO Ground Supply voltage PLL Control input Test interface Active filter output Tristate charge pump output Lock-indication output (open collector) Input of internal oscillator/buffer Output of internal oscillator/buffer Threshold voltage of comparator Charge-pump output of comparator, AGC input for amplifier and mixer Intermediate frequency output Supply voltage RF input (inverted) RF input Control input Supply voltage
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Functional Description
The U2730B-N is an L-band down-converter circuit covering a gain-controlled amplifier, a gain-controlled mixer, an output buffer, a gain control circuitry, an L-band oscillator and a frequency synthesizer block. Designed for applications in a DAB receiver, the circuit down-converts incoming L-band signals in the frequency range of 1452 MHz to 1492 MHz to an IF frequency in a range of 190 MHz to 230 MHz which can be handled by a subsequent DAB tuner. A block diagram of this circuit is shown in Figure 1.
Gain-controlled Amplifier RF signals applied to the 'RF' input pin are amplified by a gain-controlled amplifier. The
complementary pin NRF is not internally blocked, it is recommended to block this pin carefully by an external capacitor. The gain-control voltage is generated by an internal gain-control circuitry. The output signal of this amplifier is fed to a gain-controlled mixer.
Gain-controlled Mixer and Output Buffer
The purpose of this mixer is to down-convert the L-band signal in the frequency range of 1452 MHz to 1492 MHz to an IF frequency in the range of about 190 MHz to 230 MHz. Like the amplifier, the gain of the mixer is controlled by the gain-control circuitry. The IF signal is buffered and filtered by a one-pole low-pass filter at a 3 dB frequency of about 500 MHz, and then it is fed to the single-ended output pin IF. The gain-control circuitry measures the signal power, compares it with a certain power level and generates control voltages for the gain-controlled amplifier and mixer. An equivalent circuit of this functional block is shown in Figure 6. In order to meet this functionality, the output signal of the buffer amplifier is weakly band-pass filtered (transition range of about 60 MHz to 550 MHz), rectified, low-pass filtered and fed to a comparator whose threshold can be defined by an external resistor, RTH, at pin TH. By varying the value of this resistor, a power threshold of about -33 dBm to -20 dBm can be selected. In order to achieve a good intermodulation ratio, it is recommended to keep the power threshold below -25 dBm. An appropriate application is shown in Figure 3. Depending on the selection made by the comparator, a charge pump charges or discharges a capacitor which is applied to the AGC pin. By varying this capacitor, different time constants of the AGC loop can be realized. The voltage arising at the AGC pin is used to control the gain setting of the gain-controlled amplifier and mixer. The voltage at pin AGC is in the range of 5.75 V for maximum gain and 0.3 V for minimum gain. This voltage can be use to control a dual-gate GaAs-FET in front of the U2730B-N to achieve an extended AGC range. By applying an external voltage to the AGC pin, the internal AGC loop can be overdriven.
Gain-control Circuitry
Voltage-controlled Oscillator
A voltage-controlled oscillator supplies a LO signal to the mixer. An equivalent circuit of this oscillator is shown in Figure 7. In the application circuits Figure 8 and Figure 9, a ceramic coaxial resonator is applied to the oscillator's TANK and VREF pins. It should be noted that Vref has to be blocked carefully. Figure 9 shows a different application where the oscillator is overdriven by an external oscillator. In any case, a DC path at a low impedance must be established between the TANK and VREF pins. The output signal of the oscillator is fed to the LO divider block of the frequency synthesizer unit which locks the VCO's frequency on the frequency of a reference oscillator. Figure 5 shows the typical phase-noise performance of the oscillator in locked state.
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Overall Properties of the Signal Path Power Save Mode
The overall gain of this circuit amounts to 24 dB, the gain-control range is about 30 dB. With a new AGC concept in the amplifier and mixer, the U2730B-N reaches better intermodulation distances (DIM3) at higher IF output power levels. For VPSM > 2 V (pin 1) the power consumption in the analog part (gain-controlled amplifier and mixer and gain-controlled circuitry) is reduced by 80%. The VCO and the PLL is not influenced by the power-down mode. The frequency synthesizer block consists of a reference oscillator, a reference divider, a LO divider in order to divide the frequency of the internal oscillator, a tri-state phase detector, a lock detector, a programmable charge pump, a loop filter amplifier, a control interface and a test interface. The control interface is accessed by three control pins, CI, SI1 and SI2. The test interface provides test signals which represent output signals of the reference and the LO divider. The purpose of this unit is to lock the frequency fVCO of the internal VCO on the frequency fref of the reference signal applied to the input pin OSCB phase-locked loop according to the following relation: fVCO = SF fref /SFref where: SF = 2464, SFref is the scaling factor of the reference divider according to Table 1 Table 1. Scaling Factors of the Reference Frequency
Voltage at Pin SI1 GND GND GND OPEN OPEN OPEN VCC VCC VCC Voltage at Pin SI2 OPEN VCC GND OPEN VCC GND OPEN VCC GND SFref 36 33 48 65 63 64 35 32 49 Reference Oscillator Frequency 18.432 MHz - 24.576 MHz - - 32.768 MHz 17.920 MHZ 16.384 MHz -
Frequency Synthesizer
Reference Oscillator
An on-chip crystal oscillator generates the reference signal which is fed to the reference divider. By connecting a quartz crystal to pins OSCE and OSCB according to Figure 10, this oscillator generates a highly stable reference signal. The U2731B (Atmel's one-chip front-end IC) offers the reference signal at pin FREF. This reference signal (LC-filtered to suppress harmonics) can be used to overdrive the oscillator. In this application (see Figure 11) the reference signal has to be applied to the pin OSCB and the pin OSCE must be left open.
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Reference Divider
Nine different scaling factors of the reference divider can be selected by different voltage settings at the input pins SI1, SI2: 32, 33(1), 35, 36, 48, 49(1), 65(1), 64, 63(1). The reference divider factors result in reference oscillator frequencies shown in Table 1.
Note: 1. These scaling factors result in an output frequency of the reference divider of 512 kHz. If harmonics of the Bd. 3 VCO are falling in the L-band reception band, this spurious can influence the AGC of U2730B-N. That could be a problem for small incoming signals. In this case it is possible to switch the reference divider from nref to nref+1.
LO Divider
The LO divider is operated at the fixed division ratio 2464. Assuming the settings described in the section "Reference Divider", the oscillator's frequency is controlled to be 1261.568 MHz in locked state and the output frequency of the RF divider is 512 kHz. The tri-state phase detector causes the charge pump to source or to sink current at the output pin PD depending on the phase relation of its input signals which are provided by the reference and the RF divider respectively. By means of the control pin CI, two different values of this current can be selected, and furthermore the charge-pump current can be switched off. The input of the high-gain amplifier (output pin CD) which is implemented in order to construct a loop filter, as shown in the application circuit, can be switched to GND by means of the control pin CI (see Table 2). In the application circuit, the loop filter is completed by connecting the pins PD and CD by an appropriate RC network.
Phase Comparator, Charge Pump and Loop Filter
Lock Detector
An internal lock detector checks if the phase difference of the input signals of the phase detector is smaller than approximately 250 ns in seven subsequent comparisons. If a phase lock is detected, the open collector output pin PLCK is set to HIGH. It should be noted that the output current of this pin must be limited by external circuitry as it is not limited internally. If the voltage at the control pin CI is chosen to be half the supply voltage, or if this control pin is left open, the lock-detector function is deactivated and the logical value of the PLCK output is undefined. If the input control pin CI is left open (high impedance state), a test signal which monitors the output frequency of the reference divider appears at the output pin TI. In analogy to the reference divider a test signal which monitors the output frequency of the RF divider appears at the test interface output pin TI if the input control pin CI is connected to VCC/2. Table 2. Control Interface (CI) Settings
CI GND Vs VCC/2 Open PD 200 A 300 A 0 A Connected to GND PLCK ok ok Undefined Undefined TI - - RF divider Reference divider
Test Interface
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Absolute Maximum Ratings
Parameters Supply voltage RF input voltage Voltage at pin AGC Voltage at pin TH Input voltage at pin TANK (internal oscillator overdriven) Current at IF output Reference input voltage (diff.) Control input voltage PLCK output current PLCK output voltage Junction temperature Storage temperature Pins 3, 9, 20 and 28 25 and 26 18 17 5 19 15 1, 2, 10 and 27 14 14 Symbol VCC VRF VAGC VTH VTANK IIF OSCB CI, SI1, SI2, PD IPLCK VPLCK Tj Tstg Value -0.3 to +9.5 750 0.5 to 6 -0.3 to +4.0 1 4.0 1 -0.3 to +9.5 0.5 -0.3 to +5.5 125 -40 to +125 Unit V mVpp V V Vpp mA Vpp V mA V C C
Operating Range
Parameters Supply voltage Ambient Temperature Pins 3, 9, 20 and 28 Symbol VCC Tamb Value 8 to 9.35 -40 to +85 Unit V C
Thermal Resistance
Parameters Junction ambient SSO28 (mod.) Symbol RthJA Value 50 Unit K/W
Electrical Characteristics
Operating conditions: VCC = 8.5 V, Tamb = 25C, see application circuit (Figure 8), unless otherwise specified
No. Parameters Supply current (max. gain) Supply current (min. gain) Supply current (power save mode) Amplifier Mixer Pin 26 Maximum conversion gain Minimum conversion gain AGC range Third order 2 tone intermodulation ratio pRF1 + pRF2 = -10 dBm pRF1 + pRF2 = -15 dBm pRF = -60 dBm pRF = -15 dBm Test Conditions pRF = -60 dBm VPSM < 0.5 V pRF = -10 dBm VPSM < 0.5 V pRF = -10 dBm VPSM > 2 V 26 (R) 19 gc,max gc,min Dgc dim3 28 30 35 20 24 -8 32 35 40 dB dB dB dB dB A B A B A Pin Symbol IS,MAX IS,MIN IS,PD Min. Typ. 40 41 20 Max. 48 50 24 Unit mA mA mA Type* A B A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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Electrical Characteristics (Continued)
Operating conditions: VCC = 8.5 V, Tamb = 25C, see application circuit (Figure 8), unless otherwise specified
No. Parameters DSB noise figure (50-W system) RF Input Frequency range Maximum input power Input impedance IF Output Frequency range Output impedance Voltage standing wave ratio Gain Control Threshold adjustment External resistor pRF = -10 dBm VAGC = 3.5 V pRF = -60 dBm VAGC = 3.5 V pRF = -10 dBm pRF = -60 dBm 18 18 5 fLO 1 kHz distance VCO over-driven, see "Application Circuit" (Figure 8) L1kHz pLO,MIN pLO,MAX 1000 1261.568 -75 -11 -5 1500 MHz dBc/Hz dBm dBm C C C 17 18 RTH ICP,P ICP,N VAGCmin VAGCmax 5.5 75 -125 100 100 -100 0.1 5.75 125 -75 0.6 kW A A V V D A A A A 19 fout,IF Zout,IF VSWRIF 150 50 2.0 250 MHz W C D D dim3 20 dB Test Conditions Maximum gain Minimum gain 26 fin,RF pin,max,RF Zin,RF 1400 -6 200 || 1 1550 MHz dBm W || pF C C D Pin Symbol NF Min. Typ. 10 30 Max. Unit dB dB Type* D
Charge pump current
Minimum gain control voltage Maximum gain control voltage VCO Frequency Phase noise Minimum input power Maximum input power Frequency Synthesizer RF divide factor
SF SI1 = GND, SI2 = GND SI1 = GND, SI2 = VCC SI1 = GND, SI2 = open SI1 = VCC, SI2 = GND SI1 = VCC, SI2 = VCC SI1 = VCC, SI2 = open SI1 = open, SI2 = GND SI1 = open, SI2 = VCC SI1 = open, SI2 = open 15 15 Single-ended
2464 48 33 36 49 32 35 64 63 65 5 300 2.7k || 2.5 50 30 MHz mVrms mVrms kW || pF
A
Reference divide factor
SFref
A
Input frequency range Input sensitivity Maximum input signal Input impedance
fref Vrefs Vrefmax Zref
C C C D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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Electrical Characteristics (Continued)
Operating conditions: VCC = 8.5 V, Tamb = 25C, see application circuit (Figure 8), unless otherwise specified
No. Parameters Phase Detector Pin CI connected to GND Charge-pump current Output voltage PD Internal reference frequency Typical tuning voltage range Lock Indication PLCK Leakage current Saturation voltage Control Inputs SI Pin connected to GND Input voltage Control Input CI Pin connected to GND Input voltage Pin connected to VCC/2 Pin open Pin connected to VCC Test Interface TI Reference test frequency LO test frequency Voltage swing Power-save Mode PSM
PSM not active PSM active
Test Conditions
Pin 13
Symbol IPD2 IPD1 IPD1,tri
Min. 160 240
Typ. 200 300
Max. 240 360 100 0.3
Unit A A nA V kHz V A V VCC VCC VCC VCC
Type* A A A A B C A A A A A A A A A B B C
Pin CI connected to VCC Pin CI connected to VCC/2 Pin CI open, Pin 13 12 14 VPLCK = 5.5 V IPLCK = 0.25 mA 2 and 27
VPD fPD Vtune IPLCK VPLCK,sat VL VM VH 0.9 0 0.5 open 0.9 512 512 400 0 open 0.3 512
5 10 0.5 0.1 1 0.1
Pin open Pin connected to VCC 10
VL VM Vopen VH 11 ftest,ref ftest,LO Vsw 1 VPSM VPSM
1
VCC kHz kHz mVpp
Pin CI open Pin CI = VCC/2 Rload 1 MW, Cload 15 pF, Pin CI open or VCC/2
0.6 2.0
V V
A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Example: reference divider factor = 35, fREF = 17.92 MHz, charge-pump current = 200 A
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U2730B-N
Gain Control Charateristics
Operating conditions: VCC = 8.5 V, Tamb = 27C, fRF = 1490 MHz, FLO = 1261.568 MHz Figure 3. IF Output Power (Pin 19)
-10
-15
-20
pIF (dBm)
-25
Rth = 100 kW
-30
-35
-40 -60 -50 -40 -30 -20 -10 0
pRF (dBm)
Figure 4. Gain Control Voltage (Pin 11)
6
5
Rth = 100 kW
4
VAGC (V)
3
2
1
0 -60 -50 -40 -30 -20 -10 0
pRF (dBm)
11
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Phase-noise Performance
Measurement conditions: Values acquired at Pin 19 with HP 70000 spectrum analyzer. RF input (Pin 26) is blocked with 100 pF to GND. A low phase-noise signal generator (Marconi 2042) was taken as PLL reference.
Figure 5. Phase-noise Performance operating Conditions: fREF = 17.92 MHz, -10 dB, IPD = 200 A
RL -29.29 dBm ATTEN 10 dB 10.00 dB/DIV
< -75 dBc/Hz
Center 1.261 568 GHz
RB 100 Hz VB 100 Hz
Span 50.00 kHz ST 15.00 sec
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U2730B-N
Equivalent Circuits
Figure 6. AGC Control Circuit
Gaincontrolled mixer Gaincontrolled amplifier VRef1
550 MHz IF output 60 MHz VRef2
AGC
TH Rth
Figure 7. VCO Circuit
VTune 47k BBY51 VCC
1.8 p 15 p Resonator 1p VREF TANK
100 p
Resonator: Ceramic coaxial resonator Murata 3 x 3 mm, 1.6 GHz DRR030 KE1R600TC
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Figure 8. Application Circuit
VAGC
3.3 mF
8.5 V
100 pF 100 pF
RF
8.5 V
100 pF
IF
1 nF
100K 18 pF
100 pF 10 nF 100 pF 10 nF 1 nF 33 pF
Quartz
crystal
68 pF
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC4 SI1
RF
NRF GND GND GND GND VCC3
IF
AGC
TH OSCE OSCB
U2730B-N
PSM
1
SI2 VCC1 VREF TANK GND GND GND VCC2
2 3 4 5 6 7 8 9
CI
10
TI
11
CD
12
PD PLCK
13 14
Power save
100 pF 1 pF 10 nF 10 nF *100 pF 56K
5V
Lock indication
100 pF 100 pF 8.5 V 1.8 pF 8.5 V 1 nF
47K 1 nF 15 pF D1
1K *3.3 nF
1K *3.3 nF
* optional
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Application Circuit for External LO Signal
With an external LO signal it is possible to overdrive the VCO. In this case, the internal VCO acts as a LO buffer. Figure 9. Application Circuit for External LO Signal
ext. LO signal (50 W signal gen.) PLO = -10 dBm 50 TANK 100 p 470 nH VREF 1n
Figure 10. Reference Oscillator Operation
68 pF OSCB Reference devider
33 pF OSCE Quartz crystal 18 pF
Figure 11. Rerference Oscillator Overdriven
OSCB Reference signal L1 C1 OSCE Reference devider
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Ordering Information
Extended Type Number Package Remarks
U2730B-NFS U2730B-NFSG1
SSO28 SSO28
Tube Taped and reeled according to IEC 286-3
Package Information
Package SSO28
Dimensions in mm
9.10 9.01 5.7 5.3 4.5 4.3
1.30 0.25 0.65 8.45 28 15 0.15 0.05 6.6 6.3 0.15
technical drawings according to DIN specifications
1
14
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U2730B-N
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4719A-DAB-05/03 xM

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